In conventional testing of memory device, an external tester supplies control signals such as column address (CAS), row address (RAS), write enable (WE), address signals, and data to the device under test. Outputs from the device under test are sampled by the tester to determine whether the device passes or fails. As memory device density increases, testing time also increases. This increased testing time increases the manufacturing cost of integrated circuit memory devices.
In order to decrease the time it takes to test high density memory devices, parallel read and write schemes have been implemented. One drawback of implemented parallel read and write schemes is that an external tester is required. Also, parallel leads required to test the memory devices in parallel occasionally fail due to cross talk among the leads.
To avoid the drawbacks of parallel read and write schemes, built-in self-test arrangements have been used. The built-in self-test arrangement includes a read only memory that stores test algorithm instructions. The read only memory eliminates the need for external testers as well as parallel leads. Many different tests can be run in a built-in self-test arrangement. Since storage space for a built-in self-test arrangement is limited, it is desirable to write test algorithms as compact as possible. Many test require a pattern to be written to a memory array followed by the inverse of that pattern. However, current schemes lack the ability to efficiently repeat a test with the data inverted. Therefore, it is desirable to repeat a self-test with different data.